5 Key Takeaways from the RISC-V Roadshow in Boston

by Dan Mandell | 04/02/2019



The RISC-V Roadshow made its way to the Boston area yesterday, featuring a number of live demonstrations and presentations from RISC-V Foundation members. A variety of companies are participating in the North America leg of the trip, including Andes Technology, Antmicro, Dover Microsystems, Hex Five, Imperas Software, Microchip Technology, SiFive, and Western Digital. The RISC-V open-source hardware instruction set architecture has generated considerable backing in the past 18 months and now comprises more than 235 member organizations creating a collaborative community of hardware and software providers. At the event, several important themes highlighted the growing traction behind RISC-V for IoT and embedded engineering projects.

1. Open Source Opens a Lot of Doors

One of the greatest appeals of the RISC-V ISA is that it is open source and has grown a strong ecosystem for support worldwide. The RISC-V Foundation has established several groups for support (technical, marketing, education, etc.) and members have the ability to drive standards and set direction on future specifications. RISC-V is also bridging partnerships with other open source organizations, such as the Linux Foundation, to leverage their services and support. In general, the openness of the RISC-V ISA offers a lot of flexibility and configurability for the development of a wide range of computing solutions.

2. Simple is Sweet

The simplicity of RISC-V cores today enables developers to have greater control over embedded hardware development. Other architectures are rich in features but not all of those features are necessary for many applications placing needless overhead on the system. Compared to established ISAs, relatively simple RISC-V processor cores feature generally lower power consumption while enabling more configurability for microarchitectures such as for hardware control of memory.

3. Acceleration is Not Without (ISA/User) Extensions

Computing acceleration has evolved dramatically through the past several years from specialized peripherals, to co-processors, ISA expansion, and user extensions. RISC-V features a special interface, known as the ROCC interface, to help attach accelerators in a loosely coupled transaction model and is ideal for light semantic operations. Organizations like Andes Technology are building their own custom extensions to enable greater automation and capabilities for scalar and vector instructions as well as standard and custom operands.

4. Compliance & Verification are Critical

Open ISAs like RISC-V need to pioneer compliance collectively as opposed to established ISAs, which are controlled by single companies that are motivated to ensure that all designs being shipped work correctly. If RISC-V devices are built that do not comply with the foundation’s specifications, then developers would therefore not be able to assume that tools, operating systems, and application software will be transferrable and work across devices. The RISC-V Compliance Suite, which is aimed at addressing this obstacle, is still a work in progress with organizations like Imperas Software pushing new tools and solutions for verification and simulation.

5. Hardware Security is Not Created Equal

Embedded security has traditionally been built through separation, but that strategy is facing growing challenges given the number of software libraries leveraged in today’s projects. The security hardware of other processor architectures typically divides resources between two domains (a secure and an unsecure partition), hardcoded in hardware. The RISC-V Privileged Specification, however, features hardware-enforced, software-defined domains for standard RISC-V cores. Members such as Hex Five are also making available open source trusted execution environments, such as its RISC-V MultiZone Security to accelerate hardware-enforced separation for RISC-V.

The emergence of RISC-V has made hardware cool again in the embedded industry and we are excited to continue tracking its ecosystem development leading to the publication of our RISC-V in IoT study publishing in Q3. The roadshow will continue to carry on through Austin, Irvine, and the Bay Area before heading to China in early May.

View the 2019 IoT & Embedded Technology Research Outline.



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