As the embedded processor industry struggles with managing power consumption, semiconductor start-up SuVolta, based in Los Gatos, CA, has recently announced its PowerShrink low-power platform. This product, containing SuVolta’s Deeply Depleted Channel technology, will potentially reduce supply voltage on the order of 30% with no loss in performance and could bring active power consumption down by 50%. The technology also allows for reductions in “leakage” power consumption on the order of 80%, a critical breakthrough since as devices are scaling smaller, the percentage of leakage power relative to dynamic power is increasing significantly. Hence, SuVolta’s technology offers one possible solution to this hindrance.
Another advantage of this new transistor technology is on the manufacturing level. PowerShrink devices do not require new retooling or building of brand new fabrication facilities in order to construct it. The technology is based on current CMOS design standards and processes. The present fabs can be used because no new equipment is needed.
A third aspect is that due to its dynamic body biasing, it can reduce temperature and aging effects. This body biasing also reduced threshold voltage variation, which is crucial to bringing down power consumption.
What does this all mean for the embedded community? Primarily, due to the reduced power consumption, designers and developers can expand the complexity of applications for mobile devices. In fact, companies such as Fujitsu Semiconductor are licensing the technology to use this technology in their static random-access-memory (SRAM) products as well as other mobile devices. For now, this technology will be used in 65-nm products, though it will likely scale further in the future.