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Moore’s Law – Where Do We Go From Here? (Part 2)

by Eric Gulliksen | 12/31/2012

A few days ago, I posed the above question in a blog on these pages – and answered it, at least to a degree, by talking about single-atom transistors.  Although one (count it – one) has actually been made, the technology is a long way from being ubiquitous.

However, like global warming and climate change, the single-atom “wall” is real. And we are rapidly approaching it. Use of GPUs for general-purpose computing is a hedge against the wall; these have far more transistors than conventional CPUs and facilitate parallel computing. IntelNVIDIA and AMD are all pursuing this approach to supercomputing. But this isn’t a long-term solution; GPUs are faced with the same wall.

Intel is pushing toward the Moore’s law limit through cooperative efforts with several outside firms. Intel has invested a staggering US$ 4.1 billion in ASML, a Dutch semiconductor equipment manufacturer. The investment will ultimately yield Intel a 15% share of ASML, and provides US$ 3.3 billion for R&D to make “extreme ultra-violet lithography” orEUVL (using super-short wavelengths of UV light for the etching process) practical, and to develop 450-mm wafers (as opposed to today’s 300-mm wafers). The former will enable 10-nm processes, while the latter will reduce manufacturing costs. And Intel isn’t the only one; Samsung has followed suit with an investment in ASML, and Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has also made a significant investment. TSMC purports to be the world’s largest independent semiconductor factory, and, although they are currently building three 300-mm wafer fabs, their current production is limited to 200-mm.

Increasing transistor density by shrinking their size is only one way of battling the approaching wall. TSMC and one of its rivals, GlobalFoundries (GloFo), as well as Intel and the rest of the usual suspects, are actively pursuing 3-D chip technology. 3-D chips have been made; Intel’s Ivy Bridge architecture utilizes 3-D technology. 3-D transistors, calledFinFETs, promise to both increase speed and reduce power consumption.

3-D ICs

3-D integrated circuits, which will allow far greater transistor density in a given planar footprint, are on their way. However, fabrication of these is not a trivial matter. Early versions comprised stacking dice atop one another with an insulating layer between, and interconnecting the dies using a rather laborious process. This was called “Chip Stack MCM,” and didn’t produce a “real” 3-D chip. But, by 2008, 3-D IC technology had progressed to the point that four types had been defined, as follows:

(1)          Monolithic, wherein components and their interconnections were built in layers on a single wafer which was then diced into 3-D chips. This technology has been the subject of a DARPA grant, with research conducted at Stanford University.

(2)          Wafer-on-Wafer, wherein components are built on separate wafers, which are then aligned, bonded and diced into 3-D ICs. Vertical connections comprise “through-silicon vias” (TSVs) which may either be built into the wafers before bonding or created in the stack after bonding. This process is fraught with technical difficulties, not the least of which is relatively low yield.

(3)          Die-on-Wafer, where components are built on two wafers. One is then diced, with the individual dice aligned and bonded onto sites on the second wafer. TSV creation may be done either before or after bonding. Additional layers may be added before the final dicing.

(4)          Die-on-Die, where components are built on multiple dice which are then aligned and bonded. TSVs may be created either before or after bonding.

There are obvious technical difficulties and pitfalls, no matter which approach is used. These include yield factors (a single defective dice may make an entire stack useless; thermal concerns (caused by the density of components; difficulty of automating manufacture; and a lack of standards.

In my layman’s opinion, a new approach to 3-D technology may be needed before it becomes truly viable. Currently components are built on wafers through the selective removal of material. Construction of 3-D chips could be simplified through selective deposition of material rather than its removal. However, that’s beyond today’s state-of-the-art.

As we look at biological equivalents, though, it’s very clear that brains are 3-D structures. I doubt that true artificial intelligence can be realized in a relatively small package without the development of true 3-D chips. Moore’s law will ultimately stymie continued development of planar chip technology.

Stay tuned for part 3 – there’s a really interesting development out there!

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